/**
*     Copyright (c) 2025, Nsing Technologies Inc.
* 
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* referred to as Nsing). This software, and the product of Nsing described herein 
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/**
*\*\file main.c
*\*\author Nsing
*\*\version v1.0.0
*\*\copyright Copyright (c) 2025, Nsing Technologies Inc. All rights reserved.
**/

#include "n32h49x_cordic.h"
#include "n32h49x_dma.h"
#include "n32h49x_it.h"
#include "log.h"


/* Size of data array */
#define ARRAY_SIZE         (64U)

/* Max residual error in Q1.31 format */
#define MAX_RESIDUAL_ERROR_19 ((int32_t)0x00001000) /* Max residual error for sines, with 6 cycle precision: \
                                                       2^-19 max residual error, ie 31-19=12 LSB, ie <0x1000 */
#define MAX_RESIDUAL_ERROR_18 ((int32_t)0x00002000) /* Max residual error for sines, with 6 cycle precision: \
                                                       2^-18 max residual error, ie 31-18=13 LSB, ie <0x2000 */

CORDIC_InitType CORDIC_InitStructure;

/* Array of input data in Q1.31 format, regularly incremented from 0 to 2*pi */
static int32_t aInData[ARRAY_SIZE] =
{
    0x00000000, 0x04000000, 0x08000000, 0x0C000000,
    0x10000000, 0x14000000, 0x18000000, 0x1C000000,
    0x20000000, 0x24000000, 0x28000000, 0x2C000000,
    0x30000000, 0x34000000, 0x38000000, 0x3C000000,
    0x40000000, 0x44000000, 0x48000000, 0x4C000000,
    0x50000000, 0x54000000, 0x58000000, 0x5C000000,
    0x60000000, 0x64000000, 0x68000000, 0x6C000000,
    0x70000000, 0x74000000, 0x78000000, 0x7C000000,
    0x80000000, 0x84000000, 0x88000000, 0x8C000000,
    0x90000000, 0x94000000, 0x98000000, 0x9C000000,
    0xA0000000, 0xA4000000, 0xA8000000, 0xAC000000,
    0xB0000000, 0xB4000000, 0xB8000000, 0xBC000000,
    0xC0000000, 0xC4000000, 0xC8000000, 0xCC000000,
    0xD0000000, 0xD4000000, 0xD8000000, 0xDC000000,
    0xE0000000, 0xE4000000, 0xE8000000, 0xEC000000,
    0xF0000000, 0xF4000000, 0xF8000000, 0xFC000000
};

/* Array of reference result in Q1.31 format */
static int32_t aRefResult[ARRAY_SIZE] =
{
    0x00000000, 0x0C8BD35E, 0x18F8B83C, 0x25280C5D,
    0x30FBC54D, 0x3C56BA70, 0x471CECE6, 0x5133CC94,
    0x5A827999, 0x62F201AC, 0x6A6D98A4, 0x70E2CBC6,
    0x7641AF3C, 0x7A7D055B, 0x7D8A5F3F, 0x7F62368F,
    0x80000000, 0x7F62368F, 0x7D8A5F3F, 0x7A7D055B,
    0x7641AF3C, 0x70E2CBC6, 0x6A6D98A4, 0x62F201AC,
    0x5A827999, 0x5133CC94, 0x471CECE6, 0x3C56BA70,
    0x30FBC54D, 0x25280C5D, 0x18F8B83C, 0x0C8BD35E,
    0x00000000, 0xF3742CA2, 0xE70747C4, 0xDAD7F3A3,
    0xCF043AB3, 0xC3A94590, 0xB8E3131A, 0xAECC336C,
    0xA57D8667, 0x9D0DFE54, 0x9592675C, 0x8F1D343A,
    0x89BE50C4, 0x8582FAA5, 0x8275A0C1, 0x809DC971,
    0x80000000, 0x809DC971, 0x8275A0C1, 0x8582FAA5,
    0x89BE50C4, 0x8F1D343A, 0x9592675C, 0x9D0DFE54,
    0xA57D8667, 0xAECC336C, 0xB8E3131A, 0xC3A94590,
    0xCF043AB3, 0xDAD7F3A3, 0xE70747C4, 0xF3742CA2
};

/* Array of CORDIC calculated result in Q1.31 format */
static int32_t aCalResult[ARRAY_SIZE];


/**
*\*\name    RCC_Configuration.
*\*\fun     Initialization Configuration RCC.
*\*\param   none
*\*\return  none
**/
void RCC_Configuration()
{
    /* Enable DMA1 and CORDIC clock */
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPHEN_CORDIC | RCC_AHB_PERIPHEN_DMA1, ENABLE);
    /* When enabling CORDIC, HCLK DIV2 must be configured */
    RCC_ConfigPeriphClk(RCC_PERIPH_HCLK_DIV2);
}

/**
*\*\name    NVIC_Configuration.
*\*\fun     Initialization Configuration NVIC.
*\*\param   none
*\*\return  none
**/
void NVIC_Configuration()
{
    NVIC_InitType NVIC_InitStructure;
    
    /* Configures the priority group */
    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
    /* Configures the DMA1_Channel1_IRQn NVIC */
    NVIC_InitStructure.NVIC_IRQChannel                   = DMA1_Channel1_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelCmd                = ENABLE;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRE_PRIORITY_0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority        = NVIC_SUB_PRIORITY_0;
    NVIC_Init(&NVIC_InitStructure);

    /* Configures the DMA1_Channel2_IRQn NVIC */
    NVIC_InitStructure.NVIC_IRQChannel                   = DMA1_Channel2_IRQn;
    NVIC_Init(&NVIC_InitStructure);
}

/**
*\*\name    DMA_ReadConfiguration.
*\*\fun     DMA Read Channel Configuration.
*\*\param   SrcAddr :
*\*\          - Source Addresses.
*\*\param   DstAddr :
*\*\          - Destination Addresses.
*\*\param   DataLen :
*\*\          - Length of data.
*\*\return  none
**/
void DMA_ReadConfiguration(uint32_t SrcAddr, int32_t *DstAddr, uint32_t DataLen)
{
    DMA_InitType DMA_InitStructure;

    /* Reset DMA1 channel 1 */
    DMA_DeInit(DMA1_CH1);
    /* Initialize the DMA parameter structure */
    DMA_StructInit(&DMA_InitStructure);
    DMA_InitStructure.PeriphAddr     = SrcAddr;
    DMA_InitStructure.MemAddr        = (uint32_t)DstAddr;
    DMA_InitStructure.Direction      = DMA_DIR_PERIPH_SRC;
    DMA_InitStructure.BufSize        = DataLen;
    DMA_InitStructure.MemoryInc      = DMA_MEM_INC_ENABLE;
    DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD;
    DMA_InitStructure.MemDataSize    = DMA_MEM_DATA_WIDTH_WORD;
    /* Initialize DMA1 channel 1 */
    DMA_Init(DMA1_CH1, &DMA_InitStructure);
    /* CORDIC read channel mapping */
    DMA_RequestRemap(DMA_REMAP_CORDIC_RD, DMA1_CH1, ENABLE);
    /* Enable DMA1 channel 1 transfer completion interrupt */
    DMA_ConfigInt(DMA1_CH1, DMA_INT_TXC, ENABLE);
    /* Enable DMA1 channel 1 */
    DMA_EnableChannel(DMA1_CH1, ENABLE);
}

/**
*\*\name    DMA_WriteConfiguration.
*\*\fun     DMA Write Channel Configuration.
*\*\param   SrcAddr :
*\*\          - Source Addresses.
*\*\param   DstAddr :
*\*\          - Destination Addresses.
*\*\param   DataLen :
*\*\          - Length of data.
*\*\return  none
**/
void DMA_WriteConfiguration(int32_t *SrcAddr, uint32_t DstAddr, uint32_t DataLen)
{
    DMA_InitType DMA_InitStructure;
    /* Reset DMA1 channel 2 */
    DMA_DeInit(DMA1_CH2);
    /* Initialize the DMA parameter structure */
    DMA_StructInit(&DMA_InitStructure);
    DMA_InitStructure.PeriphAddr     = DstAddr;
    DMA_InitStructure.MemAddr        = (uint32_t)SrcAddr;
    DMA_InitStructure.Direction      = DMA_DIR_PERIPH_DST;
    DMA_InitStructure.BufSize        = DataLen;
    DMA_InitStructure.MemoryInc      = DMA_MEM_INC_ENABLE;
    DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD;
    DMA_InitStructure.MemDataSize    = DMA_MEM_DATA_WIDTH_WORD;
    /* Initialize DMA1 channel 2 */
    DMA_Init(DMA1_CH2, &DMA_InitStructure);
    /* CORDIC write channel mapping */
    DMA_RequestRemap(DMA_REMAP_CORDIC_WR, DMA1_CH2, ENABLE);
    /* Enable DMA1 channel 2 transfer completion interrupt */
    DMA_ConfigInt(DMA1_CH2, DMA_INT_TXC, ENABLE);
    /* Enable DMA1 channel 2 */
    DMA_EnableChannel(DMA1_CH2, ENABLE);
}

/**
*\*\name    CheckResidualError.
*\*\fun     Check delta between two values is below threshold.
*\*\param   VarA :
*\*\          - First input variable.
*\*\param   VarB :
*\*\          - Second input variable.
*\*\param   MaxResErr :
*\*\          - Maximum delta allowed between VarA and VarB.
*\*\return  status:
*\*\          - 1: Delta is below threshold
*\*\          - 0: Delta is above threshold
**/
uint32_t CheckResidualError(int32_t VarA, int32_t VarB, uint32_t MaxResErr)
{
    uint32_t status = 1U;
    if ((VarA - VarB) >= 0)
    {
        if ((VarA - VarB) > MaxResErr)
        {
            status = 0U;
        }
    }
    else
    {
        if ((VarB - VarA) > MaxResErr)
        {
            status = 0U;
        }
    }
    return status;
}

/**
*\*\name    main.
*\*\fun     Main program.
*\*\param   none
*\*\return  none 
**/
int main(void)
{
    __IO uint32_t i;
    uint32_t rRegAddr;
    uint32_t wRegAddr;

    log_init();
    
    log_info("CORDIC_Fixed_Sin_DMA demo go...\n");

    /* Clocks Configuration */
    RCC_Configuration();

    /* NVIC configuration */
    NVIC_Configuration();

    /* Module reset */
    CORDIC_DeInit();

    /* Get CORDIC read register (CORDIC_RDAT) address */
    rRegAddr = CORDIC_GetRegisterAddr(CORDIC_AS_DMA_SRCADDR);
    /* Get CORDIC write register (CORDIC_WDAT) address */
    wRegAddr = CORDIC_GetRegisterAddr(CORDIC_AS_DMA_DSTADDR);

    CORDIC_StructInit(&CORDIC_InitStructure);
    /* Select sine function */
    CORDIC_InitStructure.Function   = CORDIC_FUNCTION_SINE;
    /* Set max precision for Q1.31 sine */
    CORDIC_InitStructure.Precision  = CORDIC_PRECISION_6CYCLES;
    /* Enable Coordinate Limit */
    CORDIC_InitStructure.CodinLimit = CORDIC_CODIN_LIMIT_ENABLE;
    /* Enable Phase Limit */
    CORDIC_InitStructure.PhaseLimit = CORDIC_PHASE_LIMIT_ENABLE;
    /* Configure CORDIC */
    CORDIC_Init(&CORDIC_InitStructure);

    /* Configure DMA read channel */
    DMA_ReadConfiguration(rRegAddr, aCalResult, ARRAY_SIZE);
    /* Enable CORDIC DMA read request */
    CORDIC_DMAReadRequestCmd(ENABLE);

    /* Configure DMA write channel */
    DMA_WriteConfiguration(aInData, wRegAddr, ARRAY_SIZE);
    /* Enable CORDIC DMA write request */
    CORDIC_DMAWriteRequestCmd(ENABLE);

    /* Before starting a new process, you need to check the current state of the peripheral;
    if it's busy you need to wait for the end of current transfer before starting a new one.
    For simplicity reasons, this example is just waiting till the end of the process, but 
    application may perform other tasks while transfer operation is ongoing. */
    while (CORDIC_GetFlagStatus(CORDIC_FLAG_RRF) == RESET)
    {
        /* Do nothing */
    }
    
    /* Compare CORDIC results to the reference values */
    for (i = 0; i < ARRAY_SIZE; i++)
    {
        /* Check the data results sequentially */
        if (CheckResidualError(aCalResult[i], aRefResult[i], MAX_RESIDUAL_ERROR_18) == 0U)
        {
            log_info("Error[%d]\n", i);
            while (1);
        }
    }

    /* Calculations meet expectations */
    log_info("CORDIC demo success!!!\n");

    while (1);
}
