/**
*     Copyright (c) 2025, Nsing Technologies Inc.
* 
*     All rights reserved.
*
*     This software is the exclusive property of Nsing Technologies Inc. (Hereinafter 
* referred to as Nsing). This software, and the product of Nsing described herein 
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* improvements to this software at any time without notice. Please contact Nsing and obtain 
* the latest version of this software before placing orders.

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* 
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* the functionality and safety of any application made of this information and any resulting product. 
* In no event shall Nsing be liable for any direct, indirect, incidental, special,exemplary, or 
* consequential damages arising in any way out of the use of this software or the Product.
*
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**/



/**
*\*\file qspi_cfg.h
*\*\author Nsing 
*\*\version v1.0.0
*\*\copyright Copyright (c) 2025, Nsing Technologies Inc. All rights reserved.
**/
#ifndef  _XSPI_CFG__
#define  _XSPI_CFG__

#include "main.h"


//#define CLOCK_DIVIDER                                6
#define CTRL1_NDF_CNT                               1024

 
#define STANDRD_SPI_FORMAT               ((uint32_t)0x00000000)
#define DUAL_SPI_FORMAT                  ((uint32_t)0x00400000)
#define QUAD_SPI_FORMAT                  ((uint32_t)0x00800000)
#define OCTAL_SPI_FORMAT                 ((uint32_t)0x00C00000)

#define TX_AND_RX                       ((uint32_t)0x00000000)
#define TX_ONLY                         ((uint32_t)0x00000400)
#define RX_ONLY                         ((uint32_t)0x00000800)
#define EEPROM_READ                     ((uint32_t)0x00000c00)

#define SCPOL_LOW                    ((uint32_t)0x00000000)
#define SCPOL_HIGH                   ((uint32_t)0x00000200)

#define START_BIT                   ((uint32_t)0x00000000)
#define MIDDLE_BIT                  ((uint32_t)0x00000100)

#define SSTE_BIT1                   ((uint32_t)0x00004000)
#define SSTE_BIT0                   ((uint32_t)0x00000000)

#define TRANS_TYPE_STANDRD          ((uint32_t)0x00000000)
#define TRANS_TYPE_STANDRD_FRF      ((uint32_t)0x00000001)
#define TRANS_TYPE_FRF              ((uint32_t)0x00000002)

#define ENSPI_ADDR_NONE          ((uint32_t)0x00000000)
#define ENSPI_ADDR_04BIT         ((uint32_t)0x00000004)
#define ENSPI_ADDR_08BIT         ((uint32_t)0x00000008)
#define ENSPI_ADDR_16BIT         ((uint32_t)0x00000010)
#define ENSPI_ADDR_24BIT         ((uint32_t)0x00000018)
#define ENSPI_ADDR_28BIT         ((uint32_t)0x0000001c)
#define ENSPI_ADDR_32BIT         ((uint32_t)0x00000020)
#define ENSPI_ADDR_40BIT         ((uint32_t)0x00000028)
#define ENSPI_ADDR_48BIT         ((uint32_t)0x00000030)
#define ENSPI_ADDR_52BIT         ((uint32_t)0x00000034)
#define ENSPI_ADDR_56BIT         ((uint32_t)0x00000038)
#define ENSPI_ADDR_60BIT         ((uint32_t)0x0000003C)

#define ENSPI_INST_L_NONE          ((uint32_t)0x00000000)
#define ENSPI_INST_L_04BIT         ((uint32_t)0x00000100)
#define ENSPI_INST_L_08BIT         ((uint32_t)0x00000200)
#define ENSPI_INST_L_16BIT         ((uint32_t)0x00000300)

#define ENSPI_WAIT_8CYCLES	 ((uint32_t)0x00004000) //WAIT_CYCLES
#define ENSPI_WAIT_4CYCLES	 ((uint32_t)0x00002000) 
#define ENSPI_WAIT_2CYCLES	 ((uint32_t)0x00001000)

#define CLK_STRETCH_EN		   ((uint32_t)0x40000000)//Enables clock stretching capability in SPI transfers.
#define CLK_STRETCH_DIS   	   ((uint32_t)0x00000000)//Enables clock stretching capability in SPI transfers.

#define DMA_TX 	0x10
#define DMA_RX  0x01

void RCC_Configuration(void);
void GPIO_Configuration(void);
void XSPI_Configuration(uint32_t frame_format,uint32_t transfer_mode,uint32_t data_frame_size,uint16_t number_data_frame,uint16_t baudr);
void DMA_Configuration(uint32_t PeripheralAddr, uint32_t MemoryAddr, uint16_t Len, uint8_t TxRx, FunctionalState NewState);
#endif
